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Home > University Relations > RISE High with Us! > Research Collaboration > URECA Projects > Design a USB2.0 controller in a Xilinx FPGA
 
Design a USB2.0 controller in a Xilinx FPGA
 

Project Description :
Code in VHDL and develop the controller in a COTS prototype. The predetermined data will reside in the PowerPC memory within the FPGA to be transferred into an USB storage device (eg. thumbdrives) and vice versa. There shall be a demonstration to showcase the successful transferring of the data. Output: Documentation of the controller design and the project archive of all the VHDL source code created and the libraries used.


Pre-requisite :